Well, things are finally happening and I actually have a schematic for the main board of the Zolatron 64 6502-based homebrew computer.
I’m not saying it’s a good schematic. And I’m certainly not claiming that it will work. But it passes the Electrical Rules Check and I don’t think I’ve missed anything out. So that’s an achievement in itself.
One thing you might have noticed is that I’ve used KiCad’s ‘global label’ feature to connect most of the signal lines. The bus feature in KiCad is horrible and this is a much neater solution.
Of course, it does rather present a false impression. There are very few wires to be seen. And I know that, when it comes to routing the tracks on the PCB layout, placing all those address and data lines is going to be a nightmare. But at least, for a while, I can bask in the apparent simplicity of it all.
So here are a few notes:
RESET: I’m using a DS1813 to perform a reset. On powering the computer, or performing a reset, the 6502’s RESB input needs to be held low for at least a couple of cycles for everything to get sorted. The DS1813 is designed precisely for this kind of task. I’ve added a pull-up resistor between the RESB line and VCC to stop RESB from floating the rest of the time.
CLOCK: Not much to see here. I’m going to be using a 1MHz oscillator until I get a bit more experience and some clue as to what I’m doing.
6502 CPU: There’s also surprisingly little to be seen here so far. Most signals either go on to the address and data buses or to the backplane connector. The main exceptions are the phase 2 clock (PHI2O) and read/write selector (RWB).
RAM/ROM DECODE: I dealt with the principal behind this in a previous post. The two outputs I’m using from this 74HC00 NAND chip control the chip enable lines on the RAM and ROM chips.
RAM: The RAM_ENABLE line from the decoder is connected to both chip enable (/CE) and output enable (/OE), both of which are active low. This might seen counter-intuitive because sometimes we want input into the chip – ie, when we’re writing to a memory location – but in this scheme the output enable is active every time the chip is used. That’s because the write mode is selected by taking write enable (/WE) low, at which point the chip simply doesn’t care about the state of /OE.
Talking of writing to the chip, the /WE line is connected to the 6502’s RWB line. This goes low when the 6502 is outputting data and is high when reading, so that works perfectly here.
ROM: I’m using a 32k EEPROM chip, the Atmel AT28C256, but making use of only the bottom 16k of it. That’s why the A14 connection on the chip is just pulled low. (I’ve used a 100Ω resistor to do this. I don’t know why, or if it’s even necessary, but there it is.)
The write enable (/WE) connection is pulled high, via a resistor, because it’s not needed. I won’t be writing the contents of the ROM while it’s on the board – that’ll be done elsewhere, so we never need write mode for the ROM here. As with the RAM chip, output enable (/OE) and chip enable (/CE) are both connected to the same ROM-ENABLE line coming from the decoder.
BACKPLANE CONNECTOR: The main thing to note here is how many of the lines are not connected. I decided to throw in a couple of decoupling caps on the power lines.
So, now I just need a few spare hours to design the board. However, before committing myself to ordering actual PCBs I’ve got a couple of other stages to go through:
- First, I need to finish the Apatco kit and get it working.
- Then I’m going to modify it to reflect the design in my schematic – and check that it’s still working!