Zolatron 64: riding the address bus

The Zolatron 64 6502-based homebrew computer has a 16-bit address bus and I want to be able to interact with it manually. How do we do that?

The answer is a front panel with switches and lights, as outlined in the last post. But it’s going to be a bit more complicated than just wiring each line of the bus to a switch and an LED.

The first question to ask is, what are we trying to achieve here? We want to be able to specify an address to either read or set the data byte at that address. That’s a pure input operation – there’s no ‘reading’ of the address bus involved. That simplifies matters. Unless…

The exception to this is if I want to be able to monitor the program flow, perhaps with single stepping, so that I can watch the addresses changing. I haven’t yet decided if I want this functionality. So let’s leave it to one side for now.

I’ve come up with a functional diagram which looks like this:

When the Run/Halt switch is in RUN mode, the two buffers will be either disabled or have their output at high-impedance. That means the tristate buffer won’t mess with the bus and the LEDs won’t attempt to follow along with what’s happening on the bus – I reckon they’d just be a meaningless blur. I might change my mind about that latter thing because part of me thinks it would be interesting to run the machine at, say, 1-2Hz. But I think that’s easily changeable later.

With the Run/Halt switch in HALT mode, both buffers are enabled. The LEDs will simply show whatever is on the address bus at any time.

The 74HC193s are interesting chips. They can act like a buffer, with the outputs mirroring the inputs. But they also have clock-type counter inputs that will increment or decrement (depending on which one you pulse) the value on the output. There are also ‘carry’ and ‘borrow’ connections so that the chips can be daisy-chained. That’s important because each chip is capable of handling only four bits, so we’ll need four of them.

Two switches not shown in the diagram are EXAMINE and DEPOSIT. Here’s a description of how these will work:

  • You set an address on the switches and press EXAMINE (a momentary switch). The data LEDs will then show the value of the byte at that address.
  • You set an address on the switches and a byte value on the data switches and press DEPOSIT (also momentary). The byte value is put into memory at the selected address.

Obviously, there’s a lot of implementation detail to be worked out in terms of how the switches connect to the 6502, RAM etc. I have a hunch flip-flops will get involved. And we’ll need some serious debouncing, so say hello to Mr Schmitt. But that’s the basic idea.

But what about those PREV and NEXT switches? The idea is that, once you’ve set an address on the main switches, flipping NEXT (another momentary switch) will increment the address by one. And PREV decrements in similar fashion. I’m thinking that using these switches should also trigger an EXAMINE.

I’m not quite sure what happens if you go beyond the limits of the addressing range, but that’s a worry for another day.

At this point, the address LEDs, which just follow the address bus, will show the current address but won’t reflect what’s on the switches. So what if you’ve used PREV or NEXT but then want to set another address with the switches?

I’m not sure about this yet. I’m thinking we might need an extra latch in there somewhere. Alternatively, the 74HC193 chips have a ‘parallel load’ input that might achieve this, being triggered when you hit EXAMINE.

If you have any thoughts, they’d be gratefully received via the comments.

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